In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high carrier mobility structures for complementary metal oxide semiconductor (CMOS) applications. Traditionally, to boost performance of NFET and PFET devices, the prior art to implement this has been to grow strain Si layers on a thick (on the order of about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilites reported for prior art heterostructures, the use of thick SiGe buffer layers has several noticeable disadvantages. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations (MDs) are from about 106 to about 108 defects/cm2 which are still too high for realistic VLSI (very large scale integration) applications. Thirdly, the nature of the prior art structures precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In view of the drawbacks mentioned above with prior art methods of manufacturing strained-Si based heterostructures in which a relaxed SiGe alloy layer remains in the structure, there is a need for developing a new and improved method that allows one to fabricate a strained Si-based heterostructure, while maintaining the standard CMOS processing procedures for standard (i.e., unstrained) Si technologies. Specifically, a new method is needed that allows for the fabrication of a strained semiconductor-on insulator-substrate (SSOI) in which the strained semiconductor layer is located directly atop an insulating layer.